Solid state imaging device

ABSTRACT

A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential.

The subject matter of application Ser. No. 10/979,707, is incorporatedherein by reference. The present application is a continuation of U.S.Ser. No. 10/979,707, filed Nov. 2, 2004, now U.S. Pat. No. 7,485,903,issued Feb. 3, 2009, which claims priority to Japanese PatentApplication No. JP 2003-375202 filed Nov. 5, 2003. The presentapplication claims priority to these previously filed applications.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to solid-state imaging devices, and moreparticularly, to a solid-state imaging device, such as a complementarymetal-oxide semiconductor (CMOS) image sensor including amplifyingelements for respective pixels.

2. Description of the Related Art

Solid-state imaging devices need a great number of pixels arranged in atwo-dimensional array fashion in a pixel array area. For example, inknown CMOS image sensors, each element of a pixel is disposed in a welland the well is electrically fixed to the periphery of the pixel arrayarea.

FIG. 12 is a circuit diagram showing an example of the arrangement of aunit pixel 100. As shown in FIG. 12, the unit pixel 100 includes aphotoelectric conversion portion 101, a transfer transistor 102, anamplifying transistor 103, a reset transistor 104, and a selectiontransistor 105. The anode of the photoelectric conversion portion 101 isgrounded. The photoelectric conversion portion 101 photo-electricallyconverts incident light into an electric charge of an electron (or apositive hole) corresponding to the amount of the incident light to beaccumulated. The source of the transfer transistor 102 is connected tothe cathode of the photoelectric conversion portion 101, and the gate ofthe transfer transistor 102 is connected to a transfer signal wire 106.Also, the drain of the transfer transistor 102 is connected to a gateinput 107 of the amplifying transistor 103. When the potential of thetransfer signal wire 106 becomes the potential of a power supply wire108 (hereinafter, referred to as an “H” level), the transfer transistor102 transfers the electric charge accumulated in the photoelectricconversion portion 101 to the gate input 107 of the amplifyingtransistor 103.

The gate of the amplifying transistor 103 is connected to the gate input107, and the drain of the amplifying transistor 103 is connected to thepower supply wire 108. Also, the source of the amplifying transistor 103is connected to the drain of the selection transistor 105. Theamplifying transistor 103 outputs a voltage corresponding to theelectric charge that is transferred by the transfer transistor 102 fromthe photoelectric conversion portion 101 to the gate input 107 to thesource side. The source of the reset transistor 104 is connected to thegate input 107 of the amplifying transistor 103, and the drain of thereset transistor 104 is connected to the power supply wire 108. Also,the gate of the reset transistor 104 is connected to a reset signal wire109. When the potential of the reset signal wire 109 becomes the “H”level, the potential of the gate input 107 is reset to the potential ofthe power supply wire 108, which is a power supply voltage.

The drain of the selection transistor 105 is connected to the source ofthe amplifying transistor 103, and the gate of the selection transistor105 is connected to a selection signal wire 110. Also, the source of theselection transistor 105 is connected to a pixel output line 111. Whenthe potential of the selection signal wire 110 becomes the “H” level,the selection transistor 105 is turned on and allows conduction betweenthe source of the amplifying transistor 103 and the pixel output line111. Pixels for respective rows are connected to the pixel output line111 in parallel. The gate of a transistor 112 connected at an end of thepixel output line 111 is biased at a constant voltage by a bias powersupply 113, and the transistor 112 operates as a constant currentsource. When the selection transistor 105 of a pixel is turned on, theamplifying transistor 103 and the constant-current transistor 102function as a source follower. Thus, a voltage that has a predeterminedpotential difference from the potential of the gate input 107 of theamplifying transistor 103 is output to the pixel output line 111.

FIG. 13 is a plan pattern view showing a pixel structure of the unitpixel 100. Referring to FIG. 13, a gate electrode 201 is disposedbetween a photoelectric conversion region (activation region) 202 of thephotoelectric conversion portion 101 and an activation region 203, andconstitutes the transfer transistor 102. The activation region 203 is adrain region of the transfer transistor 102, a source region of thereset transistor 104, and the gate input 107 of the amplifyingtransistor 103. A gate electrode 204 is disposed between the activationregion 203 and an activation region 205, and constitutes the resettransistor 104. The activation region 205 is a drain region of the resettransistor 104 and a drain region of the amplifying transistor 103.

A gate electrode 206 is disposed between the activation region 205 andan activation region 207, and constitutes the amplifying transistor 103.The activation region 207 is a source region of the amplifyingtransistor 103 and a drain region of the selection transistor 105. Agate electrode 208 is disposed between the activation region 207 and anactivation region 209, and constitutes the selection transistor 105. Theactivation region 209 is a source region of the selection transistor105, and is electrically connected to the pixel output line 111, whichis a metallic wire, at a contact part 210.

The gate electrodes 201, 204, 206, and 208 are, for example, polysiliconelectrodes. The activation region 203 and the gate electrode 206 areelectrically connected to each other via a metallic wire 213 at contactparts 211 and 212. The activation region 205 is connected to a powersupply via a metallic line (not shown) at a contact part 214. Althoughwires extending in the row direction (the lateral direction in thedrawing), that is, the transfer signal wire 106, the reset signal wire109, and the selection signal wire 110 are not illustrated in FIG. 13,the gate electrodes 201, 204, and 208 are electrically connected to thetransfer signal wire 106, the reset signal wire 109, and the selectionsignal wire 110, respectively.

Although not illustrated in FIG. 13, with the pixel structure of theunit pixel 100 as described above, the base of each of the transistors102, 103, 104, and 105 is connected to a P-well. Also, the photoelectricconversion portion 101 has an arrangement in which an N-typeimpurity-doped region is covered by a P-type impurity region formedabove thereof and a P-well. Such P-regions have the same potential andare at a ground level. A well contact part and a ground wire for fixingthe P-well at the ground level have been disposed at the periphery ofthe pixel array area. This is because that a well contact part is notdisposed inside a pixel array area in order to extremely reduce the sizeof a pixel although a well contact part is normally disposed near eachtransistor.

However, for the structure in which a well contact part is disposed onlyat the periphery of the pixel array area, if an increase in the numberof pixels increases the dimensions of P-wells of a pixel array area, itis difficult to fix the intermediate portion of the P-wells at a groundpotential. Thus, the following problems occur.

-   -   A transistor has a different threshold between the center and        periphery of a pixel array area.    -   Since a photoelectric conversion portion of a type in which an        N-type impurity region is covered by a P-type impurity region        exhibits a different potential level of the P-type impurity        region between the center and periphery of the pixel array area,        a difference between the center and periphery of the pixel array        area also appears in the saturation level.    -   When each pixel is driven, a variation in the potential of a        doped layer connected to a pixel output line and the like in the        pixel being driven causes a variation in a potential itself of a        well due to a coupling capacitance of the doped layer and the        well. Thus, when all the pixels are driven at the same time or        when the number of pixels is large, the variation in the well        potential due to the coupling capacitance is not negligible at a        portion near the center of the pixel array area where pressure        of the well potential is electrically weak.

In order to electrically fix the well potential further firmly and tosolve the above problems, a solid-state imaging device enabling wellcontact for each pixel has been suggested (for example, see JapaneseUnexamined Patent Application Publication No. 2001-332714). FIG. 14 is aplan pattern view showing a pixel structure providing a well contactpart for each pixel. In FIG. 14, parts equivalent to those in FIG. 13are represented by the same reference numerals.

As shown in FIG. 14, cutting off part of the activation region 202,which is a photoelectric conversion region, of the unit pixel 100ensures an activation region 221 for achieving well contact. Theactivation region 221, which is a well contact part, is electricallyconnected to a metallic wire 222 that supplies a ground potential andthat extends in the vertical direction (the longitudinal direction inthe drawing) at a contact part 223. The other parts are similar to thosein FIG. 13.

FIG. 15 is a sectional view taken along the line XV-XV of FIG. 14. InFIG. 15, parts equivalent to those in FIG. 14 are represented by thesame reference numerals. In the example shown in FIG. 15, a P-well 302is disposed in an N-substrate 301, and the photoelectric conversionportion 101 and the transistors 102 to 105 of the pixel are disposed inthe P-well 302. An N-region 303 is an activation region (the activationregion 203 in FIG. 14) connected to the gate electrode 206 of theamplifying transistor 103 via the metallic wire 213 at the contact part211.

The activation region 202 includes an N-type impurity region 304, a P+region 305 near the surface of the N-type impurity region 304, and aP-well 302 peripheral to the N-type impurity region 304. A P+ region 306is connected to the metallic wire 222 via the doped layer and thecontact part 223 in that order, and fixes the potential of the P-well302 at the ground potential via the metallic wire 222. Elementseparation regions 307 are disposed between a photoelectric conversionportion, transistors, and the well contact part (activation region) 221so as to electrically separate the elements from each other.

However, as described above, in order to provide the activation region221 and the element separation regions 307 for achieving well contactfor every pixel without changing the size of a pixel, the dimensions ofan activation region used for a photoelectric conversion portion andtransistors must be reduced. Thus, the characteristics, morespecifically, the saturation level and the sensitivity of a pixel arereduced by a reduction in the dimensions of the activation region. Incontrast, if the activation region 221 and the element separationregions 307 are provided without changing the dimensions of anactivation region, the size of a pixel is increased due to thedimensions of the activation region.

Although a solid-state imaging device having an arrangement in which theP-well 302 is disposed in the N-substrate 301 and each element isdisposed in the P-well 302 has been described above, a similar problemoccurs in a solid-state imaging device having an impurity having anopposite conductivity type.

SUMMARY OF THE INVENTION

In order to solve the above problems, an object of the present inventionis to provide a solid-state imaging device capable of minimizing anincrease in the dimensions of a pixel and suppressing shading of anoutput signal due to a variation in the potential of a well.

According to an aspect of the present invention, a solid-state imagingdevice includes a pixel array area including pixels arranged in wells ina two-dimensional array fashion, each of the pixels including aphotoelectric conversion portion including an activation region; areading portion for reading a signal photo-electrically converted by thephotoelectric conversion portion; and an amplifying portion foramplifying the signal read by the reading portion. The solid-stateimaging device also includes well potential fixing parts each providedin the activation region of the photoelectric conversion portion in thecorresponding pixel, the well potential fixing parts fixing therespective wells at a predetermined potential.

According to another aspect of the present invention, a solid-stateimaging device includes a pixel array area including pixels arranged inwells in a two-dimensional array fashion, each of the pixels including aphotoelectric conversion portion; a reading portion for reading a signalphoto-electrically converted by the photoelectric conversion portion;and an amplifying portion for amplifying the signal read by the readingportion. The solid-state imaging device also includes well potentialfixing parts each provided for a plurality of pixels in the pixel arrayarea, the well potential fixing parts fixing the respective wells at apredetermined potential.

The term “fixing the respective wells at a predetermined potential”means not only that the respective wells are always kept at thepredetermined potential but also that, when the potential of therespective wells varies, the potential is returned to and maintained atthe predetermined potential.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing the arrangement of aCMOS image sensor according to the present invention;

FIG. 2 is a circuit diagram showing an example of the arrangement of aunit pixel;

FIG. 3 is a plan pattern view showing a pixel structure according to afirst embodiment;

FIG. 4 is a sectional view taken along the line IV-IV of FIG. 3;

FIG. 5 is a plan view schematically showing the arrangement of a pixelarray area according to a first example of a second embodiment of thepresent invention;

FIG. 6 is a block diagram showing the relationship between a sensor chipand a signal processing chip;

FIG. 7 illustrates an output level with respect to the amount of lightof each pixel in a unit cell;

FIG. 8 is a plan view schematically showing the arrangement of a pixelarray area according to a second example of the second embodiment;

FIG. 9 is a plan view schematically showing the arrangement of a pixelarray area according to a third example of the second embodiment;

FIG. 10 illustrates interpolation of a signal of a pixel in which a wellcontact part is provided;

FIG. 11 illustrates a module-type solid-state imaging device;

FIG. 12 is a circuit diagram showing a known arrangement of a unitpixel;

FIG. 13 is a plan pattern view showing a known structure of the unitpixel;

FIG. 14 is a plan pattern view showing a known pixel structure providinga well contact part for each pixel; and

FIG. 15 is a sectional view taken along the line XV-XV of FIG. 14.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference tothe drawings.

FIG. 1 is a block diagram schematically showing the arrangement of asolid-state imaging device, such as a CMOS image sensor, according tothe present invention. Referring to FIG. 1, a pixel array area 11, avertical driving circuit 12, a shutter driving circuit 13, a correlateddouble sampling (CDS) circuit 14, a horizontal driving circuit 15, anautomatic gain control (AGC) circuit 16, an analog/digital (A/D)conversion circuit 17, a timing generator 18, and the like areintegrated on a substrate (chip) 19. Hereinafter, a semiconductor chipincluding the pixel array area 11 and the peripheral driving circuits 12to 18 mounted on the chip 19 is referred to as a sensor chip 10.

The pixel array area 11 includes pixels arranged in a two-dimensionalarray fashion. Each of the pixels includes one or more photoelectricconversion portions. A pixel output line for outputting signals of thepixels and various control lines for driving the pixels are arranged soas to correspond to the arrangement of the pixels. Each of the pixelsincludes at least a photoelectric conversion portion forphoto-electrically converting incident light to be accumulated, areading portion for reading a signal charge from the photoelectricconversion portion to a floating doped region, a reset portion forresetting the floating doped region, and an amplifying portion foramplifying the signal charge read to the floating doped region. Aspecific example of a circuit of a pixel of this type will be describedbelow.

The vertical driving circuit 12 supplies a scanning signal for selectinga row to be read from a pixel to the pixel array area 11. The shutterdriving circuit 13 selects a row of a pixel, similarly to the verticaldriving circuit 12. The shutter driving circuit 13 adjusts a drivinginterval with respect to the vertical driving circuit 12, so that anexposure time (accumulation time) for the photoelectric conversionportion can be adjusted. The CDS circuit 14 is disposed for one or morepixel columns of the pixel array area 11, and CDS-processes signals readfrom the rows selected by the vertical driving circuit 12. Morespecifically, the CDS circuit 14 receives the reset level and the signallevel from each pixel and takes a difference between the reset level andthe signal level, so that a fixed pattern noise for each pixel can beeliminated.

The horizontal driving circuit 15 sequentially selects a stored signalfor each column after CDS-processed by the CDS circuit 14. The AGCcircuit 16 amplifies the signal in the column selected by the horizontaldriving circuit 15 with a proper gain. The A/D conversion circuit 17converts an analog signal amplified by the AGC circuit 16 into a digitalsignal and outputs the digital signal outside the chip 19. The timinggenerator 18 generates various timing signals and drives the verticaldriving circuit 12, the shutter driving circuit 13, the CDS circuit 14,the horizontal driving circuit 15, the AGC circuit 16, and the A/Dconversion circuit 17.

The arrangement described above is merely an example of a CMOS imagesensor. The present invention is not limited to this. In other words,the A/D conversion circuit 17 may not be arranged in the sensor chip 10.The A/D conversion circuit 17 may be arranged for each pixel column.Only one CDS circuit 14 may be provided. A plurality of output systemsincluding the CDS circuit 14, the AGC circuit 16, and the like may beprovided.

FIG. 2 is a circuit diagram showing an example of the arrangement of aunit pixel 20. As shown in FIG. 2, the unit pixel 20 according to thisexample includes a photoelectric conversion portion 21 and fourtransistors: a transfer transistor 22, an amplifying transistor 23, areset transistor 24, and a selection transistor 25. The transfertransistor 22, the amplifying transistor 23, the reset transistor 24,and the selection transistor 25 are, for example, N-MOS transistors.However, the transfer transistor 22, the amplifying transistor 23, thereset transistor 24, and the selection transistor 25 may be P-MOStransistors, instead of N-MOS transistors.

The anode of the photoelectric conversion portion 21 is grounded. Thephotoelectric conversion portion 21 photo-electrically converts incidentlight into an electric charge of an electron (or a positive hole)corresponding to the amount of the incident light to be accumulated. Thesource of the transfer transistor 22 is connected to the cathode of thephotoelectric conversion portion 21, and the gate of the transfertransistor 22 is connected to a transfer signal wire 26. Also, the drainof the transfer transistor 22 is connected to a gate input 27 of theamplifying transistor 23. When the potential of the transfer signal wire26 becomes the potential of a power supply wire 28 (hereinafter,referred to as an “H” level), the transfer transistor 22 transfers theelectric charge accumulated in the photoelectric conversion portion 21to the gate input 27 of the amplifying transistor 23.

The gate of the amplifying transistor 23 is connected to the gate input27, and the drain of the amplifying transistor 23 is connected to thepower supply wire 28. Also, the source of the amplifying transistor 23is connected to the drain of the selection transistor 25. The amplifyingtransistor 23 outputs a voltage corresponding to the electric chargethat is transferred by the transfer transistor 22 from the photoelectricconversion portion 21 to the gate input 27 to the source side. Thesource of the reset transistor 24 is connected to the gate input 27 ofthe amplifying transistor 23, and the drain of the reset transistor 24is connected to the power supply wire 28. Also, the gate of the resettransistor 24 is connected to a reset signal wire 29. When the potentialof the reset signal wire 29 becomes the “H” level, the potential of thegate input 27 is reset to the potential of the power supply wire 28,which is a power supply voltage.

The drain of the selection transistor 25 is connected to the source ofthe amplifying transistor 23, and the gate of the selection transistor25 is connected to a selection signal wire 30. Also, the source of theselection transistor 25 is connected to a pixel output line 31. When thepotential of the selection signal wire 30 becomes the “H” level, theselection transistor 25 is turned on and allows conduction between thesource of the amplifying transistor 23 and the pixel output line 31.Pixels for respective rows are connected to the pixel output line 31 inparallel. One end of the pixel output line 31 is connected to the CDScircuit 14. The other end of the pixel output line 31 is connected to atransistor 32. The gate of the transistor 32 is biased at a constantvoltage by a bias power supply 33, and the transistor 32 operates as aconstant current source.

In the unit pixel 20 having the arrangement described above, when theselection transistor 25 of a pixel is turned on, the amplifyingtransistor 23 and the constant-current transistor 32 function as asource follower. Thus, a voltage that has a predetermined potentialdifference from the potential of the gate input 27 of the amplifyingtransistor 23 is output to the pixel output line 31.

First Embodiment

According to a first embodiment of the present invention, in asolid-state imaging device, such as a CMOS image sensor having thearrangement shown in FIG. 1, by achieving well contact in an activationregion of a photoelectric conversion portion for each pixel in the pixelarray area 11, an increase in the dimensions of a unit pixel (the sizeof a pixel) is minimized and shading of an output signal due to avariation in the potential of a well is suppressed.

FIG. 3 is a plan pattern view showing a pixel structure according to thefirst embodiment. In FIG. 3, parts equivalent to those in FIG. 2 arerepresented by the same reference numerals.

Referring to FIG. 3, a gate electrode 41 is disposed between aphotoelectric conversion region (activation region) 42 and an activationregion 43 of the photoelectric conversion portion 21, and constitutesthe transfer transistor 22. The activation region 43 is a drain regionof the transfer transistor 22, a source region of the reset transistor24, and the gate input 27 of the amplifying transistor 23. A gateelectrode 44 is disposed between the activation region 43 and anactivation region 45, and constitutes the reset transistor 24. Theactivation region 45 is a drain region of the reset transistor 24 and adrain region of the amplifying transistor 23.

A gate electrode 46 is disposed between the activation region 45 and anactivation region 47, and constitutes the amplifying transistor 23. Theactivation region 47 is a source region of the amplifying transistor 43and a drain region of the selection transistor 25. A gate electrode 48is disposed between the activation region 47 and an activation region49, and constitutes the selection transistor 25. The activation region49 is a source region of the selection transistor 25, and iselectrically connected to the pixel output line 31, which is a metallicwire, at a contact part 50.

The gate electrodes 41, 44, 46, and 48 are, for example, polysiliconelectrodes. The activation region 43 and the gate electrode 46 areelectrically connected to each other via a metallic wire 53 at contactparts 51 and 52. The activation region 45 is connected to a power supplyvia a metallic line (not shown) at a contact part 54. Although wiresextending in the row direction (the lateral direction in the drawing),that is, the transfer signal wire 26, the reset signal wire 29, and theselection signal wire 30 are not illustrated in FIG. 3, the gateelectrodes 41, 44, and 48 are electrically connected to the transfersignal wire 26, the reset signal wire 29, and the selection signal wire30, respectively.

With the pixel structure described above, according to the firstembodiment, a rectangular corner portion of the activation region 42,which is a photoelectric conversion region, of the photoelectricconversion portion 21 is evenly cut off, and the cut-off area is used asa well contact part 55. In other words, the activation region 42, whichis a photoelectric conversion region, of the photoelectric conversionportion 21 and the well contact part 55 are formed in the sameactivation region 42. The well contact part 55 is electrically connectedto a metallic wire 56 that supplies a predetermined potential, such as aground potential, and that extends in the vertical direction (thelongitudinal direction in the drawing) at a contact part 57 andfunctions as a potential fixing part.

FIG. 4 is a sectional view taken along the line IV-IV of FIG. 3. In FIG.4, parts equivalent to those in FIG. 3 are represented by the samereference numerals. In the example shown in FIG. 4, a P-well 62 isdisposed in an N-substrate 61, and the photoelectric conversion portion21 and the transistors 22 to 24 of the pixel are disposed in the P-well62. An N-region 63 is an activation region (the activation region 43 inFIG. 3) connected to the gate electrode 46 of the amplifying transistor23 via a metallic wire 53 at the contact part 51.

The activation region 42 includes an N-type impurity region 64, a P+region 65 near the surface of the N-type impurity region 64, and aP-well 62 peripheral to the N-type impurity region 64. A P+ region 66 isconnected to the metallic wire 56 via a doped layer and the contact part57 in that order, and fixes the potential of the P-well 62 at the groundpotential via the metallic wire 56. A P+impurity of a density that ishigher than the P+ region 65 near the surface of the activation region42 is implanted into the P+ region 66. This prevents an influence of thewell contact part 55 upon the activation region 42. Element separationregions 67, which are local oxidization on silicon (LOCOS), shallowtrench isolation (STI), or the like, are disposed between thephotoelectric conversion portion 21 and the transistors 22 to 24 so asto electrically separate the elements from each other.

As described above, in a solid-state imaging device having anarrangement in which well contact is achieved for each pixel, by formingthe well contact part 55 in the activation region 42 of thephotoelectric conversion portion 21 without providing an elementseparation region between the well contact part 55 and the activationregion 42 of the photoelectric conversion portion 21, a part requiredfor an element separation region in the known technology can be used forthe activation region 42 of the photoelectric conversion portion 21.This arrangement reduces a burden on other elements due to provision ofthe well contact part 55.

More specifically, when the well contact part 55 is formed in theactivation region 42 of the photoelectric conversion portion 21 in orderto achieve well contact for every pixel without changing the size of thepixel, the dimensions to be cut off from the activation region 42 can bereduced compared with the known technology. Thus, a reduction in thecharacteristics, more specifically, reductions in the saturation leveland the sensitivity of the pixel can be minimized. As a result of this,since the potential of the P-well 62 can be fixed electrically firmly,an increase in the dimensions of a unit pixel (the size of a pixel) canbe minimized, and shading of an output signal due to a variation in thepotential of a well can be suppressed.

Although a solid-state imaging device having an arrangement in which theP-well 62 is formed in the N-substrate 61 and each element is formed inthe P-well 62 have been described in the first embodiment, a solid-stateimaging device having an impurity whose conductivity type is oppositecan achieve similar advantages.

Second Embodiment

According to a second embodiment of the present invention, in asolid-state imaging device, such as a CMOS image sensor having thearrangement shown in FIG. 1, by achieving well contact for a pluralityof adjoining pixels, instead of for each pixel, a reduction in thecharacteristics, more specifically, reductions in the saturation leveland the sensitivity of the pixel can be suppressed. Specific exampleswill be described below.

FIRST EXAMPLE

FIG. 5 is a plan view schematically showing the arrangement of a pixelarray area 11A according to a first example of the second embodiment.Here, in order to simplify the drawing, the pixel array area 11A has apixel arrangement of five rows and six columns.

As shown in FIG. 5, in the pixel array area 11A according to the firstexample, a plurality of adjoining pixels, for examples, four pixels,pixels 20A to 20D, constitute a unit cell 70A. A well contact part 71 isprovided in the unit cell 70A for the pixels 20A to 20D without changingthe size of each pixel. More specifically, rectangular corners, whichare adjacent to each other, of the pixels 20A to 20D are evenly cut off,and the well contact part 71 is formed at the intermediate portion ofthe pixels 20A to 20D. Also, well potential fixing wires 72 eachsupplying a well potential to the well contact part 71 are arranged inevery two columns (or every two rows), and are each electricallyconnected to the well contact part 71.

As the well contact part 71, an activation region for achieving wellcontact for each pixel may be provided separately from an activationregion of a photoelectric conversion portion and an element separationregion may be provided to separate such activation regions, as in theknown technology. Alternatively, an activation region for achieving wellcontact for each pixel may be provided in an activation region of aphotoelectric conversion portion, as in the first embodiment.

As described above, by providing the well contact part 71 in the unitcell 70A constituted by a plurality of adjoining pixels without changingthe pixel size, the well potential can be fixed further firmly andevenly compared with a known technology in which well contact isachieved only around the periphery of the pixel array area 11A. Also,since the well contact part 71 is formed by cutting off parts of theplurality of pixels (four pixels in this example), the dimensions of apart of each pixel cut off due to the provision of the well contact part71 are reduced compared with a case where a well contact part isprovided for each pixel. Thus, a reduction in the characteristics, morespecifically, reductions in the saturation level and the sensitivity ofthe pixel can be minimized.

However, since four different patterns of pixel shapes, which are due todifferences in the positions of parts that are cut off in order toprovide the well contact part 71, among the pixels 20A to 20D and theexistence of the well potential fixing wires 72 make the opticalcharacteristics different depending on the column (or the row) throughwhich the well potential fixing wire 72 passes. As a result of this, theexistence of pixels of four different types of characteristics in thepixel array area 11A needs correction that is different depending on theshape of a pixel for each row and column by a signal processing systemdownstream.

The signal processing system for performing the correction will bedescribed. As shown in FIG. 6, a signal processing chip 80 forperforming the correction is provided for the sensor chip 10 (seeFIG. 1) on which the pixel array area 11A and peripheral drivingcircuits are mounted. The signal processing chip 80 supplies clocks andcontrol signals to the sensor chip 10 and drives each pixel in the pixelarray area 11A. The signal processing chip 80 also creates picture data,as described below, by using signals output from the sensor chip 10.

Only signals of levels corresponding to electron numbers that arephoto-electrically converted at respective pixels are output from thesensor chip 10 at predetermined intervals. The signal processing chip 80performs coding with respect to the arrangement of the output signalsusing red (R), green (G), and blue (B) and makes sensitivities that aredifferent depending on the color equal to each other by applying a gainin order to create picture data. Also, with respect to a pixelexhibiting an abnormal output value in the sensor chip 10, the signalprocessing chip 80 records an address of a particular pixel in advancein a memory (not shown) contained in the signal processing chip 80,reads and abandons a signal output from the particular pixel, andaverages and weights peripheral pixel signals filtered by the samecolor, so that an output signal of the pixel is created and output. Withrespect to a vertical line and a horizontal line, the signal processingchip 80 also performs correction by applying a gain to a signal of a rowand column, the gain being different from that for the other rows andcolumns. Accordingly, in addition to creation of a picture, correctionand interpolation can be achieved.

In the pixel array area 11A according to the first example, although thepixels 20A to 20D are arranged at a predetermined interval, the shapesof the pixels are different from each other. Thus, when signals areoutput, a difference in the pixel characteristics, such as a differencein the saturation level and a difference in the sensitivity, may appearin a picture. Also, a difference in the sensitivity is caused dependingon the existence or absence of the well potential fixing wire 72 (seeFIG. 5). Since the difference in the saturation level and the differencein the sensitivity are fixed based on the shape of a pixel, thedifferences can be eliminated by knowing the amount of correction forthe differences in advance and by adjusting a gain to be applied to eachpixel signal by the signal processing chip 80 downstream in accordancewith the amount of correction.

FIG. 7 illustrates an output level with respect to the amount of lightof each of the pixels 20A to 20D in the unit cell 70A. The sensitivitiesof the pixels 20A and 20C are lower than those of the pixels 20B and 20Ddue to the existence of the well potential fixing wire 72. Also, sincethe dimensions of the pixels 20A to 20D are equal to each other, thesaturation levels of the pixels 20A to 20D are equal to each other. Thedifference in the sensitivities between the pixels 20A and 20C and thepixels 20B and 20D appears as the difference in the level betweencolumns when a picture is viewed. In order to eliminate the differencein sensitivities, the signal processing chip 80 applies a gain tosignals of the pixels 20A and 20C, and performs clip at a saturationlevel of the pixels 20B and 20D (a broken line in FIG. 7). Accordingly,the sensitivities can be set to the same value, and the saturationlevels can be set to the same value.

SECOND EXAMPLE

FIG. 8 is a plan view schematically showing the arrangement of a pixelarray area 11B according to a second example of the second embodiment.In FIG. 8, parts equivalent to those in FIG. 5 are represented by thesame reference numerals. Here, in order to simplify the drawing, thepixel array area 11B also has a pixel arrangement of five rows and sixcolumns.

In the pixel array area 11B according to the second example, fourpixels, the pixels 20A to 20D, constitute a unit cell 70B and the wellcontact part 71 is provided for the pixels 20A to 20D, as in the pixelarray area 11A according to the first example. Thus, an advantagesimilar to the first example can be achieved. In addition, in the pixelarray area 11B according to the second example, in order to ensure thespace for the well contact part 71, the ratio of dimensions of cut-offparts of the plurality of pixels is changed. Thus, a disadvantage of thefirst example in which a plurality of pixel patterns are generated by anarrangement in which parts having equal dimensions are cut off from aplurality of pixels in order to ensure the space for the well contactpart 71 can be overcome.

In the pixel array area 11B according to the second example, thedimensions of the well contact part 71 are associated only with thepixel 20A. Thus, the left pixels 20B to 20D have a structure similar toa known pixel not provided with a well contact part. Also, the pixel 20Ahas a sensitivity and a saturation level lower than the pixels 20B to20D having a different shape from the pixel 20A since the pixel 20A isinvolved in the provision of the well contact part 71.

Although, in the pixel array area 11B according to the second example,the well potential fixing wires 72 are arranged between pixel columns(or may be arranged between pixel rows), if the well potential fixingwires 72 are arranged on pixels, as in the first example, differences inthe sensitivity and the saturation level occur between a pixel throughwhich the well potential fixing wire 72 passes and a pixel through whichthe well potential fixing wire 72 does not pass. The sensitivities canbe set to the same value and the saturation levels can be set to thesame value by the signal processing chip 80 downstream (see FIG. 6), asin the first example.

THIRD EXAMPLE

FIG. 9 is a plan view schematically showing the arrangement of a pixelarray area 11C according to a third example of the second embodiment. InFIG. 9, parts equivalent to those in FIG. 5 are represented by the samereference numerals. Here, in order to simplify the drawing, the pixelarray area 11C also has a pixel arrangement of five rows and sixcolumns.

In the pixel array area 11C according to the third example, four pixels,the pixels 20A to 20D, constitute a unit cell 70C, as in the first andsecond examples. Also, in a portion, for example, to which the pixel 20Abelongs of the unit cell 70C, the well contact part 71 is provided,without providing a pixel itself. A signal for the pixel correspondingto the portion to which the pixel 20A belongs is generated by averagingsignals from pixels peripheral to the portion to which the pixel 20Abelongs by the signal processing chip 80 downstream (see FIG. 6). Thepixels 20B to 20D, which are other than the portion to which the wellcontact part 71 belongs, each has dimensions equal to a known pixel notprovided with a well contact part.

Although, in the pixel array area 11C according to the third example,the well potential fixing wires 72 are also arranged between pixelcolumns (or may be arranged between pixel rows), if the well potentialfixing wires 72 are arranged on pixels, as in the first example,differences in the sensitivity and the saturation level occur between apixel through which the well potential fixing wire 72 passes and a pixelthrough which the well potential fixing wire 72 does not pass. Thesensitivities can be set to the same value and the saturation levels canbe set to the same value by the signal processing chip 80 downstream(see FIG. 6), as in the first example.

FIG. 10 illustrates interpolation of a signal of a pixel in which thewell contact part 71 is provided. In FIG. 10, normal pixels arerepresented using a background of white, and pixels in which the wellcontact parts 71 are provided are represented using a background ofoblique lines. Information on a pixel having the background of obliquelines is obtained by calculating the average of information on, forexample, eight pixels peripheral to the pixel. For example, in FIG. 10,pixel information B1 is obtained by calculating the average ofinformation on the eight peripheral pixels A1 to A8, in other words,(A1+A2+ . . . A8)/8.

Although information on a pixel in which the well contact part 71 isprovided is interpolated by using information on the eight peripheralpixels in the third example, the present invention is not limited tothis. Information on a pixel in which the well contact part 71 isprovided may be interpolated by using at least information on pixels inthe same row or the same column as the pixel in which the well contactpart 71 is provided or at least information on pixels in the same rowand the same column as the pixel in which the well contact part 71 isprovided.

Although, in the first to third examples described above, the wellcontact part 71 is provided for the four pixels, the pixels 20A to 20D,and parts of a plurality of pixels or a part of a pixel is cut off inorder to ensure the space for the well contact part 71, the presentinvention is not limited to this. The ratio of the existence of the wellcontact part 71 or the ratio of pixels involved in the provision of thewell contact part 71 may be changed. Also, the dimensions of a well forwhich the well contact part 71 is provided, a pixel in which theprovision of the well contact part 71 is involved, and the like aredetermined in accordance with the burden of correction for a differencein the pixel shape by the signal processing chip 80 downstream, theamount of reduction of the characteristics per pixel, and the like.

Although, in the first to third examples described above, correction ofa signal of a pixel in which the well contact part 71 is provided isperformed, by the signal processing chip 80, outside the sensor chip 10,the present invention is not limited to this. A function of the signalprocessing chip 80 may be installed in the downstream of the A/Dconversion circuit 17 of the sensor chip 10, so that correction can beperformed inside the sensor chip 10.

Although cases where a solid-state imaging device according to thepresent invention is formed as a chip have been explained, the presentinvention is also applicable to a module-type imaging device or camera.FIG. 11 illustrates a module-type solid-state imaging device formed asan aggregation of a plurality of chips. The solid-state imaging deviceincludes a sensor chip for capturing images, a signal processing chipfor performing digital signal processing, and the like. Furthermore, thesolid-state imaging device may include an optical system. In this case,the characteristics of a video signal from such a module-type imagingdevice are improved.

The solid-state imaging device according to each of the first and secondembodiments of the present invention can be used as an imaging devicefor a camera module, such as a digital still camera or a video camera.The solid-state imaging device can also be used as an imaging device fora portable terminal, typified by a cellular telephone set having acamera function.

What is claimed is:
 1. A solid-state imaging device comprising: a pixelarray area including pixels arranged in second conductivity type wellregions in a two-dimensional array fashion, each of the pixelsincluding: a photoelectric conversion portion including an activationregion; and a first impurity region of a first conductivity type and asecond impurity region of a second conductivity type provided over thefirst impurity region; well potential fixing parts for fixing the secondconductivity type well regions at a predetermined potential; wherein thephotoelectric conversion portion includes a first impurity region of afirst conductivity type and a second impurity region of a secondconductivity type provided over the first impurity region, and whereinthe well potential fixing parts have an activation region connected eachconnect to a metal wiring from an upper portion of the secondconductivity type well region and a third impurity region of secondconductivity type, wherein: the photoelectric conversion portionincludes a first impurity region of a first conductivity type and asecond impurity region of a second conductivity type provided on thefirst impurity region and the well potential fixing parts are located ina part of a corresponding photoelectric conversion portion; and each ofthe well potential fixing parts includes an impurity region of thesecond conductivity type whose density is higher than the secondimpurity region.
 2. The solid-state imaging device according to claim 1,wherein each of the pixels further includes at least one or moretransistors for transferring an image signal produced by thephotoelectric conversion portion to an external device.
 3. Thesolid-state imaging device according to claim 1, wherein each of thepixels further includes at least one or more transistors for amplifyingan image signal produced by the photoelectric conversion portion.
 4. Thesolid-state imaging device according to claim 1, wherein each of thewell potential fixing parts is provided in a position among the pixels.5. The solid-state imaging device according to claim 1, furthercomprising a signal processing area for generating information on thepixel in which the corresponding well potential fixing part is providedin accordance with information on peripheral pixels.
 6. The solid-staleimaging device according to claim 5, wherein the peripheral pixels arepixels belonging to the same row as the pixel, pixels belonging to asame column as the pixel, or pixels belonging to the same row and thesame column as the pixel.
 7. The solid-state imaging device of claim 1,wherein the first impurity region for the photoelectric conversionportion extends continuously from the photoelectric conversion portionto the well potential fixing part for a given pixel.
 8. The solid-stateimaging device of claim 1, wherein the first impurity region for thephotoelectric conversion portion is located between the well potentialfixing part for a given pixel and a gate electrode of the readingportion.